(1). Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of reducing the bird's beak in the field oxide region of active devices.
(2). Description of the Prior Art
Further miniaturization of semiconductor devices continues to result in further decreases of the dimensions of device features to the point where sub-micron device features are becoming common in the design of semiconductor devices. The active area of a semiconductor substrate typically contains many active devices or device features in close physical proximity to each other, these devices or device features must be electrically isolated from each other in order to function as independent entities. Among the most frequently used methods to achieve this electrical isolation are the Localized Oxidation Isolation (LOCOS) method, the poly-buffered LOCOS (PBLOCOS) and the Shallow Trench Isolation (STI) method.
STI techniques can use a variety of methods. For instance, one method is to form shallow trenches using Buried Oxide (BOX) isolation. The method involves filling the trenches with a chemical vapor deposition (CVD) silicon oxide (SiO.sub.2), the silicon oxide is then etched back or mechanically/chemically polished to yield a planar surface. The shallow trenches that are etched for the BOX process are anisotropically plasma etched into the silicon substrate and are typically between 0.5 and 0.8 micrometer (um.) deep. STI's are formed around the active device to a depth between 4000 and 20000 Angstrom.
Another approach in forming STI's is to deposit silicon nitride on thermally grown oxide. After deposition of the nitride, a shallow trench is etched into the substrate using a mask. A layer of oxide is then deposited into the trench so that the trench forms an area of an insulating dielectric layer that acts to isolate the devices in a chip and thereby reduces the cross talk between the active devices. The excess deposited oxide is removed and the trench is planarized to prepare for the next level of metalization. The silicon nitride is provided to the silicon to prevent polishing of the masked silicon oxide of the device. This STI technique has the advantage of having no bird's beak (a problem experienced with the LOCOS technology) and no encroachment. Also, when two devices are separated by a trench, the electrical field lines have to travel a longer distance and change direction twice, so they are considerably weakened. Therefore, trenches in sub-micrometer dimensions are adequate for isolation to prevent punch-through and latch-up phenomena. Shallow-trench techniques however are complicated while in the past LOCOS and Poly-Buffered LOCOS (PBLOCOS) have provided satisfactory results. Shallow-trench techniques are therefore only slowly being used extensively in the industry.
The LOCOS process uses the characteristic of oxygen that oxygen diffuses through silicon nitride at a very slow rate. By covering silicon (of the substrate) with a layer of silicon nitride, no oxide can grow on the silicon surface. Since nitride oxidizes at a very low rate, the silicon nitride layer will form an oxidation barrier for an extended period of time. The deposition of the layer of silicon nitride is typically preceded by first forming a layer of silicon dioxide over the surface of the substrate. This SiO.sub.2 layer forms a pad or buffer oxide and is used as a stress relieve between the silicon substrate and the overlying layer of silicon nitride. This because silicon nitride exhibits very high tensile stress when deposited over silicon. The active regions are defined and etched through the layers of SiO.sub.2 (buffer oxide) and silicon nitride. Once the pattern has been defined and etched, the underlying silicon (substrate) can be implanted using P.sup.+ or N.sup.+ dopants thereby creating self-aligned (with the etched pattern) channel stop regions in the silicon substrate. It is generally desired to deposit a heavy layer of buffer oxide since this provides better protection to the underlying silicon substrate. A thick layer of buffer oxide however allows lateral oxidation to take place in the surface of the substrate by making the silicon nitride layer less effective as an oxidation mask. It is this lateral oxidation in the surface of the substrate that is referred to as bird's beak because this lateral oxidation, which takes place at both extremities of the openings of the created pattern, resembles the beak of a bird. The process of forming an insulating region proceeds by thermally growing the field oxide by wet oxidation (typically 450 to 850 nm thick, at a temperature of between about 550 and 950 degrees C. for a time of about 6 hours). After this process of growing the field oxide is completed, the layers of silicon nitride and buffer oxide can be removed.
The discipline of LOCOS isolation is extensively discussed in the literature of the art, for instance the publication Silicon Processing for the VLSI era, by S. Wolf, Lattice Press, Volume 2, Process Integration, chapter 2, pages 17 et al., provides detail on this subject.
It is clear that the phenomenon of the bird's beak is at cross-purposes with the design requirement of reducing device features since the bird's beak extends into the silicon substrate and thereby limits proximity of typical pattern openings. In the era of sub-micron device features, a typical bird's beak extends around about 0.5 um on each side of the pattern opening. Several schemes have been tried to reduce the size of the bird's beak, these schemes relate to selecting the relative thickness of the buffer oxide layer and the overlying layer of silicon nitride. It has been proposed to use materials other than oxide for the buffer layer, for instance a poly-buffered pad layer can be created for stress relieve. The invention addresses such a solution whereby a layer of silicon-oxynitride-oxide (SXO) is used to serve as buffer stress release layer while at the same time serving to shorten the typical bird's beak. For the prevention of the recessed bird's beak, SXO provides better results than SOON.
U.S. Pat. No. 5,616,401 (Kobayashi et al.) (cited by the inventor) shows a method comprising: form pad dielectric layer of oxynitride continuity film (SOON) using a N.sub.2 O, SiH.sub.4 and NH.sub.3 Plasma process, form SiN, pattern, form FOX. See Koyayashi FIGS. 1 to 3, spec. col. 7 & 8; see claims. Kobayshi has a preferred SOON method using CVD and SiH.sub.2 Cl.sub.2, NH.sub.3 and N.sub.2 O, see col. 7. But is not limited to that process. The inventor distinguishes the exact process of the invention over Kobayashi by pointing out that the structure of SOON (of Kobayashi) and SXO are converse structures, that is:
1) for SOON the silicon dioxide (SiO.sub.2) composition is near the silicon substrate while the silicon nitride (SiN.sub.4) is near the Si.sub.3 N.sub.4 film. The sequence of layers for the SOON is therefore as follows: silicon (of the substrate) over which the layer of SOON (with the composition of SiO.sub.2 followed by the SiN.sub.4 as indicated ) over which the layer of Si.sub.3 N.sub.4, and
2) for SXO is a silicon oxynitride-oxide film with the silicon oxynitride (SiON) composition near the silicon substrate and the silicon oxide (SiO.sub.2) composition near the Si.sub.3 N.sub.4 film. The sequence of layers for the SXO is therefore as follows: silicon (of the substrate) over which the layer of SXO (with the composition of SiON followed by the SiO.sub.2 as indicated) over which the layer of Si.sub.3 N.sub.4.
U.S. Pat. No. 5,374,585 (Smith et al.) shows a FOX process where the pad dielectric layer can be oxynitride. See col. 2, lines 60 to 65.
U.S. Pat. No. 4,762,728 (Keyser et al.) teaches a nitridation process.